1. Field of the Invention
This invention relates to a data transfer system for transferring data in synchronization with system clock and a synchronous semiconductor memory device.
2. Description of the Related Art
Modern semiconductor device systems have been improved so as to be capable of processing large quantity data and at high data processing speed.
With this situation, the data processing speed of MPUs is getting faster at a good pace. In contrast, the data processing speed of memory devices has been improved at a slower pace than the MPUs, although their storage capacity is getting larger at a good pace. As a result, the difference in data processing speed between the MPUs and the memory devices is steadily getting wider.
To eliminated such a difference in speed, a memory device has been developed which controls the operation of the system by a method different from the control method of conventional memory devices and thereby improves the data transfer rate. This is a synchronous memory device. A typical synchronous memory device is a dynamic RAM that is controlled in synchronization with the system clock.
Hereinafter, this type of dynamic RAM is referred to as a synchronous DRAM in this specification and is abbreviated as an SDRAM. The basic operation of an SDRAM has been disclosed in Jpn. Pat. Appln. KOKAI Publication No. 5-2873. A concrete SDRAM product was announced in SHINGAKU GIHO SDM93-142, ICD93-136 (1993-11).
In the present specification, explanation of the specifications for the SDRAM will not be given. What is important to the SDRAM is to read the serially accessed burst data as fast as possible. The specifications for the SDRAM and the architecture to realize them are roughly divided into those for a pipeline type and those for a register type.